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FAN5071
High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage Platforms
Features
* Output programmable in 25mV steps from 1.05V to 1.825V using a dynamically programmable integrated 5-bit DAC * Controls adjustable linears for Vclock (2.5V), Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), and Vadj (1.2V nominal) * Remote sense * Programmable Active DroopTM up to 200mV * Drives N-Channel MOSFETs * Overcurrent protection using MOSFET sensing * Overvoltage protection including startup * 85% efficiency typical at full load * Integrated Power Good and Enable/Soft Start functions * Linears start instantly * Meets Intel VRM8.5 specifications using minimum number of external components * 24 pin SOIC package
Description
The FAN5071 is a synchronous mode DC-DC controller IC which provides a highly accurate, programmable set of output voltages for multi-voltage platforms such as the Intel Pentium III, and provides a complete solution for all Intel VRM8.5 CPU applications, and for other high-performance processors. The FAN5071 features remote voltage sensing, independently adjustable current limit, and a proprietary wide-range Programmable Active DroopTM for optimal converter transient response and VRM8.5 compliance. The FAN5071 uses a 5-bit D/A converter to dynamically program the output voltage during operation from 1.05V to 1.825V in 25mV steps. The FAN5071 uses a high level of integration to deliver load currents in excess of 28A from a 5V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range. An on-board precision low TC reference achieves 0.8% voltage regulation without expensive external components. The FAN5071 includes linear regulator controllers for Vclock (2.5V),Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), and Vadjustable (1.2V nominal) each adjustable with an external divider. The FAN5071 also offers integrated functions including open-collector Power Good, Output Enable/Soft
Applications
* Power supply for Pentium(R) III Platforms * VRM for Pentium III processor * Programmable multi-output power supply
Block Diagram
+3.3V +5V VCCA 21 +1.2V/Adj 9 10 VCCP 11 + + REF PWRGD, OCL OCL REF +12V PWRGD, OCL OSC + 15 14 13 3.3/1.5V 5-Bit DAC 1.24V Reference Power Good 3 GNDA 16 ENABLE/SS + + 18 RS 20 24 VCCP 1 HIDRV +5V + 19 RD
12 +2.5V
Digital Control
2
VCC
V PWRGD, OCL
+
23 LODRV 22 GNDP 17 PWRGD
8765 4 VID0 VID2 VID4 VID1 VID3
Pentium is a registered trademark of Intel Corporation. Programmable Active Droop is a trademark of Fairchild Semiconductor.
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FAN5071
Start and current limiting. The linears start instantly, not waiting for softstart. The FAN5071 is available in a 24 pin SOIC package.
Pin Assignments
HIDRV SW GNDA VID4 VID3 VID2 VID1 VID0 VADJGATE VADJFB VCKGATE VCKFB 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCCP LODRV GNDP VCCA VFB DROOP ILIM PWRGD SS/ENABLE TYPEDET VAGPGATE VAGPFB
FAN5071
Pin Definitions
Pin Number 1 2 3 4-8 9 10 11 12 13 14 15 16 Pin Name HIDRV SW GNDA VID4-0 VADJGATE VADJFB VCKGATE VCKFB VAGPFB VAGPGATE TYPEDET ENABLE/SS Pin Function Description High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be <0.5". High Side Driver Source and Low Side Driver Drain Switching Node. Together with DROOP and ILIM pins allows FET sensing for VCC current. Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops. Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 1. Gate Driver for VADJ Transistor. For Adjustable output. Voltage Feedback for VADJ. Gate Driver for VCK Transistor. For 2.5V output. Voltage Feedback for VCK. Voltage Feedback for VAGP. Gate Driver for VAGP Transistor. For 3.3/1.5V output. Type Detect. Sets 3.3V or 1.5V for AGP. Output Enable. A logic LOW on this pin will disable all outputs. An internal current source allows for open collector control. This pin also doubles as soft start for the switcher. Power Good Flag. An open collector output that will be logic LOW if any output voltage is not within 14% of the nominal output voltage setpoint. VCC Current Feedback. Pin 18 is used in conjunction with pin 2 as the input for the VCC current feedback control loop. Layout of these traces is critical to system performance. See Application Information for details. Droop Set. Use this pin to set magnitude of active droop. Vcc Voltage Feedback. Pin 20 is used as the input for the VCC voltage feedback control loop. See Application Information for details regarding correct layout. Analog VCC. Connect to system 5V supply and decouple with a 0.1F ceramic capacitor. Power Ground. Return pin for high currents flowing in pin 24 (VCCP). VCC Low Side FET Driver. Connect this pin to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be <0.5". Power VCC. For all FET drivers. Connect to system 12V supply through a 33, and decouple with a 1F ceramic capacitor.
17 18
PWRGD ILIM
19 20 21 22 23
DROOP VFB VCCA GNDP LODRV
24
VCCP
2
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PRODUCT SPECIFICATION
FAN5071
Absolute Maximum Ratings
Supply Voltage VCCP to GND Supply Voltage VCCA to GND Voltage Identification Code Inputs, VID0-VID4 All Other Pins Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds Thermal Resistance Junction-to-case, 1JA
Note 1: Component mounted on demo board in free air.
15V 13.5V VCCA 13.5V 150C -65 to 150C 300C 75C/W
Recommended Operating Conditions
Parameter Supply Voltage VCCA Input Logic HIGH Input Logic LOW Ambient Operating Temperature Output Driver Supply, VCCP 0 10.8 12 Conditions Min. 4.50 2.0 0.8 70 13.2 Typ. 5 Max. 5.25 Units V V V C V
Electrical Specifications
(VCCA = 5V, VCCP = 12V, VOUT = 1.425V, and TA = +25C using circuits in Figure 1, unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter VCC Regulator Output Voltage Output Current Initial Voltage Setpoint Output Temperature Drift Line Regulation Internal Droop Output Ripple Total Output Variation, Efficiency Output Driver Rise & Fall Time Output Driver Deadtime Duty Cycle 5V UVLO 12V UVLO Soft Start Current REV. 1.0.4 1/29/02 * * Transient2 Impedance3 Maximum Programmable Droop 20MHz BW, ILOAD = 28A * * * ILOAD = 18A, VVID = 1.425V See Figure 3 See Figure 3 0 3.76 7.65 5 4 8.5 10 1.360 1.335 45 50 83 50 50 100 4.24 9.35 17 ILOAD = 0.8A to Imax, VVID = 1.425V Total Output Variation, Steady State1 VVID = 1.425V3 Short Circuit Detect Current ILOAD = 0.8A, VVID = 1.425V TA = 0 to 70C, VVID = 1.425V VIN = 4.75V to 5.25V ILOAD = 0.8A to 30A * * * 13.0 200 20 1.490 1.515 60 See Table I * 1.05 28 1.453 1.465 1.477 -6 +10 14.4 15.8 1.825 V A V mV mV/V K mV mVpk V V A % nsec nsec % V V A 3 Conditions Min. Typ. Max. Units
FAN5071
Electrical Specifications (Continued) (VCCA = 5V, VCCP = 12V, VOUT = 1.425V, and TA = +25C using circuits in Figure 1, unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range.
Parameter Adjustable Linear Regulator Output Voltage Over Current Trip Level VCLK Linear Regulator Output Voltage Over Current Trip Level VAGP Linear Regulator Output Voltage Output Voltage Over Current Trip Level Common Functions Oscillator Frequency PWRGD Threshold4 Switcher Logic HIGH [VVID + 85mV] Logic LOW [VVID-155mV] HIGH LOW All Outputs * * * * 255 88 80 6 25 80 300 345 112 120 kHz % sec mV %Vout ILOAD 2A, TYPEDET = 0V ILOAD 2A, TYPEDET = OPEN * * 1.425 3.135 1.5 3.3 80 1.575 3.465 V V %VO ILOAD 2A * 2.375 2.5 80 2.625 V %VO ILOAD 2A * 1.188 1.212 1.236 80 V %VO Conditions Min. Typ. Max. Units
PWRGD Delay Switcher PWRGD Hysteresis Switcher PWRGD Threshold4 Linear Regulators
Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is measured at the converter's VFB sense point. 2. As measured at the converter's VFB sense point. For motherboard applications, the PCB layout should exhibit no more than 0.5m trace resistance between the converter's output capacitors and the CPU. Remote sensing should be used for optimal performance. 3. Using the VFB pin for remote sensing of the converter's output at the load, and the appropriate droop, the converter will be in compliance with Intel's VRM 8.5 specification. If Intel specifications on maximum plane resistance from the converter's output capacitors to the CPU are met, the specifications at the capacitors will also be met. 4. PWRGD will be high only if BOTH the linears and the switcher conditions are met. PWRGD will be low if EITHER condition is met.
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Table 1. Output Voltage Programming Codes for FAN5071
VID25mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID3 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID2 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Nominal VOUT 1.050V 1.075V 1.100V 1.125V 1.150V 1.175V 1.200V 1.225V 1.250V 1.275V 1.300V 1.325V 1.350V 1.375V 1.400V 1.425V 1.450V 1.475V 1.500V 1.525V 1.550V 1.575V 1.600V 1.625V 1.650V 1.675V 1.700V 1.725V 1.750V 1.775V 1.800V 1.825V
Note: 1. 0 = processor pin is tied to GND. 1 = processor pin is pulled up to 3.3V.
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PRODUCT SPECIFICATION
FAN5071
Typical Operating Characteristics
(VCCA = 5V, VCCP = 12V, and TA = +25C using circuit in Figure 1, unless otherwise noted.)
Vcpu Efficiency vs.Output Current
90 1.48 Droop,Circuit of Fig.1
1.46 85 1.44 Efficiency (%) 80 Vout (V) 75 70 1.36 65 2 4 6 8 10 12 14 16 18 Output Current (A) 20 22 24 26 28 1.42
1.4
1.38
1.34 0 3 6 9 12 15 Output Current (A) 18 21 24 28
Output Ripple, 1.425 @ 28A
Transient Response, 28A to 0.1A
1.515V VCPU (20mV/div) VCPU (50mV/div)
1.425V
1.335V
Time (2s/division)
Time (20s/division)
Transient Response, 0.1A to 28A
Switching Waveforms, 28A Load
1.515V VCPU (50mV/div)
5V/div
HIDRV pin 1.425V LODRV pin 5V/div 1.335V
Time (20s/division)
Time (20s/division)
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FAN5071
Typical Operating Characteristics (continued)
Output Startup, System Power-up Output Startup from Enable
VCPU (1V/div)
VIM (2V/div)
VCPU (1V/div) ENABLE (2V/div)
Time (10ms/division)
Time (20ms/div)
Application Circuit
L1 (Optional) +5V CIN
R6 R7 R5 C2
C1
L2 VO COUT D1 VID4 VID3 VID2 VID1 VID0
Q1
R2
1 2 3 4 5 6 7 8 9 10 11 12 U1 FAN5071
24 23 22 21 20 19 18 17 16 15 14 13 C7
R1 +12V C5
Q2
R3
C3
VCC R4 PWRGD ENABLE/SS
R8-12 3.3V IN Q3
TYPEDET
C6
Q5
C4 3.3/1.5V (AGP)
1.2V C8
Q4 2.5V C9 Adjustable with an external divider.
Figure 1. Application Circuit for VRM8.5 Motherboards (Worst Case Analyzed! See Appendix for Details)
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FAN5071
Table 3. FAN5071 Application Bill of Materials for Intel VRM8.5 Motherboards
(Components based on Worst Case Analysis--See Appendix for Details) Reference C1 C2, C5 C3-4,C6 C7-9 CIN COUT D1 L1 L2 Q1 Q2 Q3-5 R1 R2-3, R6 R4, R8-12 R5 R7 U1 Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1C105ZFX Panasonic ECU-V1H104ZFX Sanyo 6MV1000FA Rubycon 16ZL1000M Rubycon 6.3ZL1500M Motorola MBRD835L Any Coiltronics HC2-1R0 Fairchild FDD6690A Fairchild FDD6680A Fairchild NDB4032L Any Any Any Any Any Fairchild FAN5071M Quantity 1 2 3 3 4 8 1 Optional 1 2 2 3 1 3 6 1 1 1 Description 4.7F, 10V Capacitor 1F, 16V Capacitor 100nF, 50V Capacitor 1000F, 6.3V Electrolytic 1000F, 16V Electrolytic 1500F, 6.3V Electrolytic 8A Schottky Diode 1.3H, 10A Inductor 1.0H, 34A Inductor N-Channel MOSFET N-Channel MOSFET N-Channel MOSFET 10 4.7 10K 27.4K 8.66K DC/DC Controller DCR ~ 6m See Note 1. DCR ~ 1m RDS(ON) = 17m @ VGS = 4.5V See Note 2. RDS(ON) = 13m @ VGS = 4.5V See Note 2. IRMS = 2.3A ESR 23m Requirements/Comments
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For 30A designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/W should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletins AB-8 and AB-15.
Test Parameters
tR 90% 10% t DT 2V 2V 90% 2V 10% tDT LODRV tF HIDRV
2V
Figure 2. Output Drive Timing Diagram
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PRODUCT SPECIFICATION
FAN5071
Application Information
The FAN5071 Controller
The FAN5071 is a programmable synchronous DC-DC controller IC. When designed around the appropriate external components, the FAN5071 can be configured to deliver more than 28A of output current, as appropriate for Intel's VRM8.5, and other processors. The FAN5071 functions as a fixed frequency PWM step down regulator.
Internal Voltage Reference
The reference included in the FAN5071 is a precision bandgap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. In the FAN5071, the DAC monitors the 5 voltage identification pins, VID0-4, and scales the voltage from 1.050V to 1.825V in 25mV steps according to Table I.
Main Control Loop
Refer to the FAN5071 Block Diagram on page 1. The FAN5071 implements "summing mode control," which is different from both classical voltage-mode and current-mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts input from the DROOP (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the output to one of the summing amplifier inputs. The second, current control path, takes the difference between the DROOP and SW pins when the high-side MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to another input of the summing amplifier. These two signals are then summed together. This output is then presented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator input and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. There is an additional comparator in the analog control section whose function is to set the point at which the FAN5071 current limit comparator disables the output drive signals to the external power MOSFETs.
Power Good (PWRGD)
The FAN5071 Power Good function is designed in accordance with VRM8.5 and DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should either of two conditions obtain: 1) any of the linear power supply voltages deviate more than -20% from their nominal setpoint; 2) The switching power supply output is more than +14% from (VVID + 80mV), or less than -14% from (VVID - 120mV). The Power Good flag provides no other control function to the FAN5071.
Output Enable/Soft Start (ENABLE/SS)
The FAN5071 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to softstart the switching. A softstart capacitor may be approximately chosen by the formula: 10A * t C = --------------------1.8V The linear regulators are not softstarted.
Over-Voltage Protection
The FAN5071 continuously monitors the output voltage for protection against over-voltage conditions. If the voltage at the VFB pin exceeds approximately 2.5V, an OVP circuit forces the low-side MOSFET on, over-riding all other conditions. The OVP circuit remains active, and the low-side MOSFET remains on, until the VFB voltage drops below approximately 2.1V. The OVP circuit is functional even during startup; thus, protection is provided even during startup with a shorted high-side MOSFET.
High Current Output Drivers
The FAN5071 contains two identical high current output drivers that utilize high speed bipolar transistors in a pushpull configuration. The drivers' power and ground are separated from the chip's power and ground for switching noise immunity. The power supply pin, VCCP, is supplied from an external 12V source through a series resistor. The resulting voltage is sufficient to provide the gate to source drive to the external MOSFETs required in order to achieve a low RDS,ON.
Oscillator
The FAN5071 oscillator section uses a fixed frequency of operation of 300KHz.
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FAN5071
PRODUCT SPECIFICATION
Design Considerations and Component Selection
Additional information on design and component selection may be found in Fairchild's Application Note 57.
MOSFET Selection
This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: * Low Static Drain-Source On-Resistance, RDS,ON < 20m (lower is better) * Low gate drive voltage, VGS = 4.5V rated * Power package with low Thermal Resistance * Drain-Source voltage rating > 15V. The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. For details and a spreadsheet on MOSFET selection, refer to Applications Bulletin AB-8.
Some margin should be maintained away from both Lmin and Lmax. Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for Co, which must be increased to increase L. Adding margin by decreasing L can be done by purchasing capacitors with lower ESR. The FAN5071 provides significant cost savings for the newer CPU systems that typically run at high supply current.
FAN5071 Short Circuit Current Characteristics
The FAN5071 protects against output short circuit on the core supply by latching off both the high-side and low-side MOSFETs. The FAN5071 short circuit current characteristic includes a hysteresis function that prevents the DC-DC converter from oscillating in the event of a short circuit. The short circuit limit is set with the RS resistor, as given by the formula
RS = ISC *RDS, on IDetect
Inductor Selection
Choosing the value of the inductor is a trade-off between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is:
(Vin - Vout) f Vout Vin ESR x Vripple
with IDetect 50A, ISC the desired current limit, and RDS,on the high-side MOSFET's on resistance. Remember to make the RS large enough to include the effects of initial tolerance and temperature variation on the MOSFET's RDS,on. Alternately, use of a sense resistor in series with the source of the MOSFET, as shown in Figure 6, eliminates this source of inaccuracy in the current limit. As an example, Figure 3 shows the typical characteristic of the DC-DC converter circuit with two FDD6690A high-side MOSFETs (RDS = 17m maximum at 25C * 1.25 at 75C = 21.25m each for a total of 10.6m) and a 6.19K RS.
Lmin =
x
where: Vin = Input Power Supply Vout = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel Vripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is:
Lmax = 2CO (Vin - Vout) Dm Vtb Ipp2
VOUT (V) 0
10
20
30
40
50
Output Current (A)
Figure 3. FAN5071 Short Circuit Characteristic
where: Co = The total output capacitance Ipp = Maximum to minimum load transient current Vtb = The output voltage tolerance budget allocated to load transient Dm = Maximum duty cycle for the DC/DC converter (usually 95%).
The converter exhibits a normal load regulation characteristic until the voltage across the MOSFET exceeds the internal short circuit threshold of 50A * 6.2K = 310mV, which occurs at 310mV/10.6m = 29A. [Note that this current limit level can be as high as 310mV/6.5m = 48A, if the MOSFET has typical RDS,on rather than maximum, and is at 25C. This is the reason for using the external sense resistor.] At this point, the internal comparator trips and signals the REV. 1.0.4 1/29/02
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PRODUCT SPECIFICATION
FAN5071
controller to reduce the converter's duty cycle to approximately 20%. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. With a 4m output short, the voltage is reduced to 29A * 4m = 116mV. The output voltage does not return to its nominal value until the output current is reduced to a value within the safe operating range for the DC-DC converter.
deliver current when the high side MOSFET switches on. Figure 4 shows 3 x 1000F, but the exact number required will vary with the speed and type of the processor. Capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter, refer to Applications Bulletin AB-15.
2.5H 5V 0.1F Vin 1000F, 10V Electrolytic
Schottky Diode Selection
The application circuits of Figure 1 shows a Schottky diode, D1, which is used as a free-wheeling diode to assure that the body-diode in Q2 does not conduct when the upper MOSFET is turning off and the lower MOSFET is turning on. It is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades efficiency, and so the Schottky provides a shunt path for the current. Since this time duration is very short, the selection criterion for the diode is that the forward voltage of the Schottky at the output current should be less than the forward voltage of the MOSFET's body diode.
Figure 4. Input Filter
Programmable Active DroopTM
The FAN5071 includes Programmable Active DroopTM: as the output current increases, the output voltage drops, and the amount of this drop is user adjustable. This is done in order to allow maximum headroom for transient response of the converter. The current is typically sensed by measuring the voltage across the RDS,on of the high-side MOSFET during its on time, as shown in Figures 1 and 2. To program the amount of droop, use the formula
RD 14.4K *Imax *Rsense VDroop *3
Output Filter Capacitors
The output bulk capacitors of a converter help determine its output ripple voltage and its transient response. It has already been seen in the section on selecting an inductor that the ESR helps set the minimum inductance, and the capacitance value helps set the maximum inductance. For most converters, however, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the ESR and not the capacitance value. That is, in order to achieve the necessary ESR to meet the transient and ripple requirements, the capacitance value required is already very large. The most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low ESR. The only type of aluminum capacitor used should be those that have an ESR rated at 100kHz. Consult Application Bulletin AB-14 for detailed information on output capacitor selection. The output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1F and 0.01F are recommended values.
where Imax is the current at which the droop occurs, and Rsense is the resistance of the current sensor, either the source resistor or the high-side MOSFET's on-resistance. For example, to get 120mV of droop with a maximum output current of 30A and a 10m sense resistor, use RD = 14.4K * 30A * 10m/(120mV *3) = 12K. The value of the product Imax*Rsense must be < 600mV for proper functioning of the droop circuit. If this product is exceeded, a lower resistance MOSFET must be used. Further details on use of the Programmable Active DroopTM may be found in Applications Bulletin AB-24.
Remote Sense Input Filter
The DC-DC converter design may include an input inductor between the system +5V supply and the converter input as shown in Figure 5. This inductor serves to isolate the +5V supply from the noise in the switching portion of the DC-DC converter, and to limit the inrush current into the input capacitors during power up. A value of 2.5H is recommended. It is necessary to have some low ESR aluminum electrolytic capacitors at the input to the converter. These capacitors The FAN5071 offers remote sense of the output voltage to minimize the output capacitor requirements of the converter. It is highly recommended that the remote sense pin, Pin 20, be tied directly to the processor power pins, so that the effects of power plane impedance are eliminated. Further details on use of the remote sense feature of the FAN5071 may be found in Applications Bulletin AB-24.
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FAN5071
PRODUCT SPECIFICATION
Adjusting the Linear Regulators' Output Voltages
Any or all of the linear regulators' outputs may be adjusted high to compensate for voltage drop along traces, as shown in Figure 5.
PCB Layout Guidelines
* Placement of the MOSFETs relative to the FAN5071 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the FAN5071 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difficult to suppress. * In general, all of the noisy switching lines should be kept away from the quiet analog section of the FAN5071. That is, traces that connect to pins 1, 2, 23, and 24 (HIDRV, SW, LODRV and VCCP) should be kept far away from the traces that connect to pins 3, 20 and 21. * Place the 0.1F decoupling capacitors as close to the FAN5071 pins as possible. Extra lead length on these reduces their ability to suppress noise. * Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins. * Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the first bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1F decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. * Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converter's performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5. * A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11.
VGATE VOUT R VFB 10K
Figure 5. Adjusting the Output Voltage of the Linear Regulator
The resistor value should be chosen as
Vout Vnom
R = 2K*
For example, to get the VADJ voltage to be 1.50V instead of 1.20V, use R = 2K * [(1.50/1.20) - 1] = 500.
Using the FAN5071 for Vnorthbridge = 1.8V
Similarly, the FAN5071 can also be used to generate Vnorthbridge = 1.8V by utilizing the AGP regulator as shown in Figure 5: tie the TYPEDET pin to ground, and use R = 399.
Coppermine/Tualatin VTT
The adjustable regulator may be used for powering VTT in systems in which either a Coppermine or a Tualatin processor may be used, as shown in Figure 6.
VGATE VTT 100 VFB 487 10K 3.16K
Additional Information
For additional information contact your local Fairchild Semiconductor representative, or visit us at our web site www.fairchildsemi.com.
10K AF36
2N7002
2N7002
Figure 6. Using VADJ to Generate VTT
12
REV. 1.0.4 1/29/02
PRODUCT SPECIFICATION
FAN5071
Appendix
Worst-Case Formulae for the Calculation of Cin, Cout, R5, R7 and Roffset (Circuits similar to Figure 1 only)
The following formulae design the FAN5071 for worst-case operation, including initial tolerance and temperature dependence of all of the IC parameters (initial setpoint, reference tolerance and tempco, internal droop impedance, current sensor gain), the initial tolerance and temperature dependence of the MOSFET, and the ESR of the capacitors. The following information must be provided: VS+, the value of the positive static voltage limit; |VS-|, the absolute value of the negative static voltage limit; VT+, the value of the positive transient voltage limit; |VT-|, the absolute value of the negative transient voltage limit;
Number of capacitors needed for COUT = the greater of:
X= VTESR * IO + VS+ - .024 * Vnom
or
ESR * IO VT+ - VS+ + 14400 * IO * RD 18 * R5 * 1.1
Y=
Example: Suppose that the static limits are +89mV/-79mV, transient limits are 134mV, current I is 14.2A, and the nominal voltage is 2.000V, using MOSFET current sensing. We have VS+ = 0.089, |VS-| = 0.079, VT+ = |VT-| = 0.134, IO = 14.2, Vnom = 2.000, and RD = 1.67. We calculate:
2
2.000 14.2 * 5 Cin = 2
-
2.000 5
IO, the maximum output current; Vnom, the nominal output voltage; Vin, the input voltage (typically 5V); Irms, the ripple current rating of the input capacitors, per cap (2A for the Sanyo parts shown in this data sheet); RD, the resistance of the current sensor (usually the MOSFET); RD, the tolerance of the current sensor (usually about 67% for MOSFET sensing, including temperature); and ESR, the ESR of the output capacitors, per cap (44m for the Sanyo parts shown in this data sheet).
2 IO * Cin = Vnom Vin Irms - Vnom Vin
= 3.47 4 caps
Roffset =
0.089 - .014 * 2.000 - .029 *1000 = 15.8 0.29 + 2.000 14.2 * 0.020 * (1 + 0.67) 45 * 10-6 = 10.5K
R7 =
R5 =
14400 * 14.2 * 0.020 * (1 + 0.67) * 1.1 18 * (0.089 + 0.079 - .024 * 2.000)
= 3.48K
X=
0.044 * 14.2 0.134 + 0.089 - .024 * 2.00 0.044 * 14.2
= 3.57
Y= 0.134 - 0.089 + 14400 * 14.2 * 0.020 18 * 3640 * 1.1
= 6.14
Roffset =
VS+ - .014 * Vnom - .029 .029 * Vnom IO* RD * (1 + RD) 45 * 10-6
Since Y > X, we choose Y, and round up to find we need 7 capacitors for COUT.
* 1K
A detailed explanation of this calculation may be found in Applications Bulletin AB-24.
R7 =
14400 * IO* RD * (1 + RD) *1.1 R5 = 18 * (VS+ + VS- - .024 * Vnom)
REV. 1.0.4 1/29/02
13
PRODUCT SPECIFICATION
FAN5071
Mechanical Dimensions
24 Lead SOIC
Symbol A A1 B C D E e H h L N ccc Inches Min. .093 .004 .013 .009 .599 Max. .104 .012 .020 .013 .614 Millimeters Min. 2.35 0.10 0.33 0.23 15.20 Max. 2.65 0.30 0.51 0.32 15.60 5 2 2 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.290 .299 .050 BSC .394 .419 .010 .016 24 0 -- 8 .004 .020 .050
7.36 7.60 1.27 BSC 10.00 10.65 0.25 0.40 24 0 -- 8 0.10 0.51 1.27
3 6
24
13
E
H
1
12
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C L
h x 45 C
REV. 1.0.4 1/29/02
14
FAN5071
Ordering Information
Product Number FAN5071M Description VRM8.5 Package 24 pin SOIC
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
1/29/02 0.0m 005 Stock#DS30005071 2001 Fairchild Semiconductor Corporation

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